Good interpersonal, organizational and communication skills.
Open-minded. Highly responsible and enthusiastic in pursuing excellence.
Huawei Technologies Co., LtdIndustry:Electronics/Micro-electronics | Company Type: | Company Size:
Company Profile:2006-7 - 2009-12 Analog IC Design Engineer
Location:Shen Zhen | Job Type:Full-time | Department: | Report to: | Number of Subordinates:employees | :
Job Category:Integrated Circuit R&D
Career Level:Mid Career(2+ years experience)cheap polo shirts
Responsibilities and Achievements:Responsibilities & Achievements:
1. Designed a 700MHz input bandwidth 200MSamples/s 11bit pipelined ADC in America. I am the owner of blocks as follow: input buffer with 700MHz -3dB bandwidth and 75dB THD@300MHz input frequency, the second stage of MDAC, and band gap circuit. This project was developed with local team in the Silicon valley of America for more than six months. We talk about the full chip scheme; ADC structure and Every difficulty we met. I also design the test scheme and evaluation board. So far, Test result met the specification. This converter is implemented in the TSMC 0.18um mix-signal process.cheap ralph lauren polo shirts
2. Developed a 20Msamples/s 10 bit 18mW dual channels pipelined ADC IP for analog baseband chip independently. For low power purpose, I implemented this ADC with different structure and different low power tricks (such as without sample hold, share OTA, low power internal reference buffer structure.). I also design some block like DAC\PLL\filter etc. This project is implemented in the SMIC 0.18 mix-signal process and has been volume production.
3. In charge of evaluation and integration of video ADC IP which provided by different famous IP vendors. Evaluated whether IP performance met our specification, how about technique support. Provided integration guideline for full chip integration and test scheme for ATE test. This project is implemented in the SMIC 0.18 mix-signal process and has been volume production.ralph lauren polo shirts
4. Created the behavioral model for pipelined ADC with Matlab. Researched different error sources (such as capacitor mismatch, OTA finite gain and bandwidth, comparator offset, KT/C noise and clock jitter.) how to affect the ADC. Verify analog and digital calibration method with matlab model.
